Over the course of months, and even years, engineering teams all over the world work together to develop advanced technologies that are years ahead of where we are today in minute-sized, application specific integrated circuits (ASIC).
It is this exciting race, filled with challenges and discoveries, that brings to life smaller, faster, and more power efficient IC designs built to innovate future technologies. Because of the robust nature of stage design, layout, and production, most manufacturers have embraced the ASIC design flow.
What is an ASIC Design Flow?
The ASIC design flow is a time-tested mature methodology that combines multiple steps to form the backbone of every ASIC design project. All IC engineers have encountered the ASIC design flow in some sequence or another.
How does the ASIC Design Flow work?
Similar to what most will refer to as “milestones”, the ASIC design cycle is separated into the frontend (planning and design) and backend stages (layout, verification and beyond). Within each of these stages, key steps include conceptualizing, developing specifications, and overcoming the challenges of producing fabrication-ready designs.
Though highly rewarding, these stages can last for months or years, depending on the specifications, resources, and engineering capacity of teams.
Who is involved in the process?
It’s important to keep in mind that when we talk about integrated circuits, we’re really talking about tiny, nanometer-sized electrical chips. Absolute design accuracy must be achieved before production can begin since printing the initial prototypes comes at an exorbitant cost.
Several teams of IC design engineers and IC Layout engineers collaborate in tandem throughout a typical ASIC design flow process (particularly for VLSI – Very Large Scale Integration).
Alongside the core teams are specialized engineers with place and route, and design verification experience who ensure the chip being produced is compatible with the larger environment, and functioning within specifications. These engineers work together with design and layout engineers throughout the stages of design and development. Companies and teams looking for ASIC design services consult with us as their experts and source of manpower to help them achieve their target specifications within their deadlines.
What are some examples of ASIC technologies?
Application specific integrated circuit technologies result in products within everyday technology. These can include:
- A chip designed to manage the communication and interface between memory chips and microprocessors in a laptop, desktop or mobile device’s CPU.
- A chip designed to control functional responses based on an input such as temperature, ambient light, and volume. These can be found inside smart ovens, smart televisions, and audiophile devices such as home entertainment systems and large scale audio networks.
- A chip designed to provide brilliant image quality in the form of a CMOS sensor. These chips consist of a digital logic and an amplifier.
Stages of ASIC Design Flow
Today, businesses that produce extensively used items or consumer products with high volume sales, such as cell phones or other comparable applications, are dominated by the ASIC Design flow.
The overall ASIC design flow, which includes several processes like design conception, chip optimization, logical/physical implementation, and design validation and verification, so far has been used in millions of ASIC designs and has proven to be both practical and reliable.
Let’s go over each of the steps involved in the process.
In this step, the engineer defines the design of the microprocessor or the system’s central component (heart), also known as “microarchitecture.” This stage also implements how the system interacts and its specifications. Two teams are included in chip specification: The Design team and the Verification team.
- Design Team: Generates RTL Code.
- Verification Team: Generates test bench.
The two described teams’ collaboration will be explained in greater detail in the following step.
Design Entry / Functional Verification
Assuming your ASIC specifications have been completed and approved by all parties, it is time to consider the architectural design.
On a design entry level, functional verification uses simulation to determine whether the circuit design in the chip specification performs well in its intended functions. Here, the design and verification teams collaborate to ensure that the simulations are accurate by running repetitive tests. This is referred to as behavioral simulation.
What is VLSI behavioral simulation?
It’s a quick simulation method, but the results are less accurate. The goal is to run an abstract form of code (RTL) through a behavioral simulation to determine what components, connections, and structures are required to physically and functionally implement that design in real time, with the objective of delivering at least 95% accuracy.
The engineers in charge of code accuracy will also use various simulation tools, such as functional simulation tools and timing simulation tools, to test the functionality and timing of the circuit, respectively.
RTL block synthesis / RTL Function
After the RTL code and test bench have been finalized and checked for accuracy, the RTL block synthesis process begins. This essentially means that from abstract lines of codes (RTL), it will be synthesized or converted into physical components of a circuit (gate-level netlist). This process is performed by a synthesis tool, which is used to ensure it meets the required timings. When these requirements are met, the design is prepared for testability, or DFT.
This is the stage in which the engineer develops the ASIC’s framework using HLL, or high level languages like C++, in accordance with the requirements and specifications of the ASIC design layout.
With careful consideration for performance, resources, and practicality, the engineers will partition the ASIC into a hierarchical block or modules. After the blocks or modules are constructed in an architectural document the ASIC design partitioning will be further planned by reusing or obtaining some part of a previously made design.
Design for Testing (DTF) insertion
At certain points in the design flow, ASIC design can be complicated. Making a mistake after production will be dreadful not only for the customer, but also the whole team, as the entire process will have to be repeated. As a result, the engineering team uses several tests to validate the design.
- Scan path insertion
Checks small parts of the design rather than the overall design by replacing sequential elements with scannable sequential elements and then connecting all the scan cells into a single long scan register called scan path.
- Memory BIST (Built-In-Self-Test)
A self-testing and repair mechanism that examines the Random Access Memories (RAMs) using an effective set of algorithms capable of detecting faults in the memory.
- ATPG (Automatic Test Pattern Generation)
Recognizes input or test patterns and differentiates between correct and faulty circuit behavior caused by circuit or component defects.
Floor Planning (blueprint your chip)
By this stage of the design flow, the gate level netlist has already been converted to a complete physical geometric representation. Now, the first step towards bringing the design to life is floorplanning, which is a process of arranging various blocks across the chip area to minimize computation latency, power consumption, chip area, and cost based on the design constraints such as block placement, design portioning, pin placement and power optimization.
To make the most of the chip’s limited space, floor-planning involves carefully placing cells. Because, without careful placement, the entire floor plan may have a negative impact on the chip’s performance in terms of timing delay and power dissipation.
What is a cell?
A cell is a group of electrical components called transistors which provides the storage capacity or the boolean logic function (Boolean Algebra is analogous to addition, subtraction, etc. but in programming standards).
Prior to Clock Tree Synthesis, each clock pin was driven by a single clock source, which caused skewness and delay. A Clock Tree Synthesis which comprises the construction and balancing of a clock tree, is a technique for decreasing the clock delay to all clock inputs. As a result, the clock connection to the clock pin of a sequential element operates efficiently while providing the necessary time and area for the overall design.
As stated previously, timing, area and efficiency are an integral part in designing the structure. In order to have the most efficient requirements as possible, there are several types of Clock tree synthesis structures that can be utilized.
A Clock Mesh structure uses a tree of drivers to divide the root clock signal into parallel paths before feeding it into a group of buffers that are cross-connected in a metal mesh, directed to the clock sinks. Because of the mesh’s cross-linking, a resonant structure is created and the delays of each mesh buffer are effectively canceled out.
The clock tree’s pre-mesh drivers can be arranged into H-trees by reassembling it into the letter H using five driver branches. While not as on-chip variation (OCV) resistant as a mesh, the H-tree design has a naturally balanced structure that minimizes skew through its inherent routing symmetry and offers superior stability over temperature and voltage corners than standard CTS.
Ideally, H-trees would be used in full CTS implementations to deliver clock signals to the actual sinks.However, routing blockages and other problems have made it challenging to put into reality because physical intervention may be required to clear blockages, which makes sign-off more difficult.
H-tree and X-tree structures are extremely similar. The only difference is that the connections between the drivers in the X-tree structure are not rectilinear like those in the H-tree. Despite having a lower delay than an H-tree construction, an X-tree structure experiences more crosstalk since the wires are placed closer together.
On the other hand, a “fishbone” structure, as its name implies, is like a spine-ribs, having smaller wirelength, latency, and clock power but larger skew than an H-tree. No previous work has enabled a systematic exploration of the system between H-tree and spine to achieve an optimal tradeoff among clock power, skew and latency.
A Hybrid Structure fills the methodology gap between conventional CTS and pure clock mesh. Pure clock mesh provides the greatest results for clock frequency, skew, and OCV, while traditional CTS provides the lowest power consumption and the simplest flow.
The Hybrid structure offers a compromise between the two methods while favoring pure clock mesh’s OCV tolerance. As a result, a wider range of designs can make use of the many advantages mesh technology has to offer.
Each structure is equal depending on the needs of the system requirements. Buffers or inverters are introduced by different optimizations to build a specific structure during clock tree synthesis with the main objective of ensuring the least possible insertion delay, skew, and chip power consumption.
The clock tree is fixed and routed after the optimizations have been completed and cannot undergo any further optimizations besides buffer or gate sizing.
After rationally placing a few million gates on the little surface area of the chip. What’s next? Routing!
Here, the physical connections are made between the cells in a way that the paths should meet the constraints such as having an optimal path and minimum number of wires and wire length.
There are three types of routing: power, clock, and signal routing. Furthermore, However, the full routing process is broken down into the following steps:
Global routing divides the entire design into small routing regions, or tiles and rectangles, and then selects a pathway from one region to another in a way that maximizes timing and wire lengths. This is merely the planning phase; no actual routing has yet been completed.
At this stage, the critical paths are identified and fixed repeatedly until they are successful.
Final Verification (Physical Verification and Timing)
Finally, the design layout of an ASIC moves into the final stages of timing, and physical verification known as signoff check. This phase is crucial since it contributes in the layout’s ability to function as envisioned by the engineers’ design. This stage goes through three processes to avoid error before being sent for manufacturing.
Layout versus schematic (LVS)
Layout versus schematic, in its simplest form, is a comparison of what is produced in an IC’s layout to the initial schematic developed by an IC Design Engineer.
Design rule checks (DRC)
The GDS file is reviewed to see if the geometric design complies with the foundry’s standards. It is a process that ensures the chip design functions as intended, taking into account all the limitations, restrictions, and rules set by the initial requirement to be compliant with the scope of work.
Logical Equivalence Checks (LEC)
It involves reviewing the design in both the pre- and post-design layout. Formal verification approaches have been developed using mathematical proof rather than simulation or test vectors to provide a higher level of verification.
GDS II – Graphical Data Stream Information Interchange
The IC engineer wraps up wafer processing, packing, testing, verification, and finally, delivery to the physical IC. The semiconductor foundries create and use the GDSII file to generate silicon and handle it for clients.
What is GDS II?
A database file format known as GDS II has become the industry standard for exchanging data for integrated circuit or IC layout artwork even though it has a limited set of capabilities and poor data density. This is because it continues to operate with frequently incompatible and proprietary data formats. The GDS II data can be utilized to rebuild all or a portion of the design to be used in sharing layouts or moving designs between tools.
A wafer is a piece of semiconductor material that is shaped like an extremely thin disc and made of silicon. This wafer is used to create integrated circuits (IC). A single wafer contains several hundreds of chips.
Packaging and Testing
Here, the wafers are examined to determine whether they meet the electrical requirements. Wafers are deemed to be in good condition after they pass specific electrical testing, whereas defective chips are scrapped. The chips that passed the first test were further examined under a microscope before being packed.
To make sure that the chips are absolutely good, it is rechecked again for verification after packaging. After the verification process, it will finally be delivered to the physical IC!
Key Highlights and Takeaways:
- Design, Layout and Verification processes and engineers are unified throughout the process by the specifications laid out during planning stages
- Before moving on to the next process, each stage of the ASIC development is thoroughly handled and validated.