Job Summary:
The Senior Analog Layout Engineer will lead the layout design and optimization of complex analog and mixed-signal integrated circuits. This role involves full ownership of the layout process, including floor planning, verification, and signoff, as well as technical leadership and mentorship for junior engineers. The ideal candidate will have deep expertise in advanced layout techniques and process technologies.

Key Responsibilities:

• Ownership of Layout Design: Lead the physical layout of large and complex analog and mixed-signal blocks, such as data converters, PLLs, power management ICs, and full-chip floor planning.
• Advanced Layout Techniques: Apply advanced layout techniques for matching, isolation, shielding, and parasitic minimization to ensure the highest performance.
• DRC/LVS Signoff: Take responsibility for the full DRC and LVS verification flow, working closely with the verification team to resolve any issues and ensure clean signoff.
• Technical Leadership: Provide mentorship and technical guidance to junior and intermediate layout engineers, sharing best practices and reviewing their work.
• Cross-Functional Collaboration: Collaborate with design engineers, verification engineers, and other stakeholders to ensure design goals are achieved.
• Post-Layout Analysis: Perform post-layout simulations and assist in debugging layout-related silicon issues during the validation phase.
• Process Optimization: Continuously seek ways to improve layout methodologies and workflows for better efficiency and quality.

Key Qualifications

• Bachelor’s degree in Electrical Engineering, Microelectronics, or related field. Master’s/PhD is a plus.
• 7+ years of experience in analog/mixed-signal IC layout, with a proven track record of leading complex layout projects and successful tape outs.
• Expert knowledge of analog layout methodologies and tools (e.g., Cadence Virtuoso).
• Strong understanding of advanced process technologies (e.g., FinFET, CMOS) and their impact on layout design.
• Experience with full-chip layout, including top-level floor planning, integration, and ESD design.
• Familiar with DRC, LVS, parasitic extraction, and post-layout simulation flows.